Function Verification of Combinational Arithmetic Circuits

FUNCTION VERIFICATION OF COMBINATIONAL ARITHMETIC CIRCUIT MAY 2015 DUO LIU B.S., JIANGNAN UNIVERSITY, WUXI, JIANGSU, CHINA M.S.E.C.E., UNIVERSITY OF MASSACHUSETTS AMHERST Directed by: Professor Maciej Ciesielski Hardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for performance is ever higher. Conventional simulation-based verification method cannot keep up with the rapid increase in the design size, since it is impossible to exhaustively test all input vectors of a complex design. An important part of hardware verification is combinational arithmetic circuit verification. It draws a lot of attention because flattening the design into bit-level, known as the bit-blasting problem, hinders the efficiency of many current formal techniques. The goal of this thesis is to introduce a robust and efficient formal verification method for combinational integer arithmetic circuit based on an in-depth analysis of recent advances in computer algebra. The method proposed here solves the verification problem at bit level, while avoiding bit-blasting problem. It also avoids the expensive Groebner basis computation, typically employed by